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esynr3z
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corsair
Control and Status Register map generator for HDL projects
https://corsair.readthedocs.io
MIT License
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#enhancement : Change rst signal according to _neg / _pos
#63
stdefeber
opened
1 week ago
0
#enhancement : Add wishbone B4 or AHB interface
#62
stdefeber
opened
1 week ago
0
#enhancement : add wishbone b3
#61
stdefeber
opened
1 week ago
0
Avalon master read fails
#60
stdefeber
opened
1 week ago
0
Verilog waccess not aligned with output data
#59
sinill57
opened
3 months ago
0
Verilog build failed when using multistring description #bug
#58
iDoka
opened
4 months ago
0
Docs update for PR#55 PR#56
#57
iDoka
opened
4 months ago
2
Add verilog template name
#56
iDoka
opened
4 months ago
1
Add asciidoc template name support
#55
iDoka
opened
4 months ago
1
Added option that will add a table to the documentation with an overview of all of the parameters that have a lock indicator
#54
willemss
opened
4 months ago
1
Fixed error when defining a reserved field at LSB position in Markdown template
#53
malsheimer
opened
8 months ago
0
c-headers: struct and bit field layout are implementation defined...
#52
v0lker
opened
1 year ago
0
allow the base address to be a string
#51
v0lker
opened
1 year ago
0
feature request: support symbolic constants for `base_address`, (do not require it to be a number)
#50
v0lker
opened
1 year ago
1
Constants and expressions support
#49
m-kru
opened
1 year ago
0
Addressing mode support
#48
m-kru
opened
1 year ago
0
Enumeration types support
#47
m-kru
opened
1 year ago
0
Interrupt support
#46
m-kru
opened
1 year ago
0
changed PSLVERR output to low (OKAY) in APB2LB template
#45
malsheimer
closed
1 year ago
1
Fixed an error that occurred in the HDL (Verilog/VHDL) templates when bit fields are defined such that it results in a 1 bit wide 'reserved' field at position MSB.
#44
malsheimer
closed
1 year ago
2
Updated Class Wavedrom() in generators.py
#43
malsheimer
closed
1 year ago
0
Cam ad
#42
malsheimer
closed
1 year ago
0
Updated class Wavedrom() in generators.py
#41
malsheimer
closed
1 year ago
0
New patch v1.0.4
#40
arnfol
closed
1 year ago
0
Memory interface support
#39
arnfol
opened
1 year ago
0
Acess mode 'roc' can miss a latch
#38
arnfol
opened
1 year ago
0
Fix/rolh miss (issue #28)
#37
arnfol
closed
1 year ago
0
fix actions
#36
arnfol
closed
1 year ago
0
bump version
#35
arnfol
closed
1 year ago
0
Fix vhdl addr constants #33
#34
arnfol
closed
1 year ago
0
VHDL target: compare parametric address to constants
#33
arnfol
closed
1 year ago
1
Queue read not working when FIFO is ready in advance
#32
arnfol
closed
1 year ago
2
base_address for RTL modules
#31
vborchsh
closed
1 year ago
2
Fix/vhdl tests (copy of #21)
#30
arnfol
closed
1 year ago
0
A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal
#29
nmmalipes
closed
1 year ago
1
Access mode 'rolh' can miss a latch
#28
nmmalipes
closed
1 year ago
2
#4: verilog/VHDL: only generate access signal for specified access mode
#27
v0lker
closed
1 year ago
0
multiple issues in C header generation (padding, masks)
#26
v0lker
closed
1 year ago
2
bugs in c header generation
#25
v0lker
closed
1 year ago
3
Optional timeout on reads and writes
#24
stridge-cruxml
opened
1 year ago
0
Move access and hardware from bitfields to reg
#23
stridge-cruxml
closed
1 year ago
2
Added argument to generators to allow passing in of custom template.
#22
stridge-cruxml
opened
1 year ago
1
Fix/vhdl tests
#21
stridge-cruxml
closed
1 year ago
2
Resolve timescale issues
#20
stridge-cruxml
closed
1 year ago
0
fix: Reading external register with 0 latency
#19
Xtyll
closed
1 year ago
1
Add generator for CMSIS SVD
#18
raffi-g
opened
2 years ago
0
Add generator for CMSIS SVD
#17
raffi-g
closed
2 years ago
0
Confusing terminology: MSB & LSB vs Offset & Width
#16
iDoka
opened
2 years ago
0
#enhancement: wavedrom bitfield adding `lanes` to csrconfig
#15
iDoka
opened
2 years ago
2
#enhancement: add gitignore which included all auto-generated files
#14
iDoka
opened
2 years ago
0
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