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esynr3z
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corsair
Control and Status Register map generator for HDL projects
https://corsair.readthedocs.io
MIT License
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#enhancement: add informative header to all auto-generated files
#13
iDoka
opened
2 years ago
0
CMSIS SVD
#12
raffi-g
opened
2 years ago
2
Add generator for reStructuredText
#11
raffi-g
opened
2 years ago
0
Fix bugs in c header
#10
raffi-g
closed
1 year ago
1
Fix struct reserved bitwidth spacing in c_template.
#9
stridge-cruxml
closed
2 years ago
1
AXI BResp and RResp
#8
stridge-cruxml
opened
2 years ago
5
Verilog AXI read queue for first word fall through fifo.
#7
stridge-cruxml
closed
1 year ago
2
Fix typo in assertion string.
#6
stridge-cruxml
closed
2 years ago
0
add disclaimer about "wo" access mode
#5
arnfol
closed
2 years ago
0
Minor bug in VHDL file generation (csr_*_ren signal)
#4
arnfol
closed
1 year ago
7
feature/spi2lb
#3
esynr3z
closed
3 years ago
0
New documentation types added
#2
EgorVorontsov
closed
2 years ago
1
Avalon-MM added
#1
evgeniyBolnov
closed
3 years ago
0
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