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### Version
Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
hlblk167_reg
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### Summary 💡
Currently in the languages section a circle using the "chip" color is printed along the programming language name, it would be more attractive to the eye to have the colored **logo** …
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## Problem
There is no Major for any HDL(Hardware Description Language)s as I see it.
Like VHDL, Verilog and SystemVerilog.
## Solution
Implement Major modes for HDLs?
## Alternatives
Develo…
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**The feature is not related to a problem**
**Describe the solution you'd like**
It would be nice to include slang (https://github.com/MikePopoloski/slang) as an additional linter to teros HDL. Cu…
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At least one tutorial uses `hdl/`, even for RTL source files that aren't exactly HDL but Verilog / SystemVerilog:
https://www.ece.ucdavis.edu/~bbaas/180/tutorials/file.organization.html
Perhaps …
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Create good support for SystemVerilog.
- [ ] https://github.com/hdl/bazel_rules_hdl/issues/132
- [ ] https://github.com/hdl/bazel_rules_hdl/issues/133
- [ ] https://github.com/hdl/bazel_rules_…
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## Branch / Commit Hash
`dev`
## Area
tools
## Current behavior
To work around tools with insufficient SystemVerilog support, a SystemVerilog-to-Verilog HDL converter is desired. BSG currentl…
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I was trying to use a "mailbox" within my SystemVerilog testbench but got the following error:
../hdl/generator.sv:3: syntax error
../hdl/generator.sv:3: error: mailbox doesn't name a type.
…
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verilog.instantiateModule
popup notifications:
Verilog-HDL/SystemVerilog:No modules found in the file
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SystemVerilog is a very popular hardware description language (HDL). Google is working on improving the ecosystem around this language, including developing linting and code fixing tooling. It would b…