Adding slang as SystemVerilog linter

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

https://terostechnology.github.io/terosHDLdoc/

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Adding slang as SystemVerilog linter #573

Open astrollo opened 5 months ago

astrollo commented 5 months ago

The feature is not related to a problem

Describe the solution you'd like It would be nice to include slang (https://github.com/MikePopoloski/slang) as an additional linter to teros HDL. Currently, slang is the most compliant SystemVerilog open source frontend.

AndrewNolte commented 3 months ago

I think slang is best positioned to be the best option for analyzing verilog because of speed and compliance. It could also be used to analyze drivers/loads, dependency tree, etc. Right now this can sort of be achieved through tying together scripts (see this exension), but I think it would be best if a proper language server were made with slang, rather than a bunch of binaries.