SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
http://peakrdl-regblock.readthedocs.io
GNU General Public License v3.0
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missing we property in struct register defenition #79

Closed nirb82 closed 10 months ago

nirb82 commented 10 months ago

When add this prop we = true; the actual logic generated in the sv file, but, no we member added to the reg field struct.

always_comb begin automatic logic [0:0] next_c = field_storage.clmgr_efuse_main_cfg0.ApbOrTdr.value; automatic logic load_next_c = '0; if(decoded_reg_strb.clmgr_efuse_main_cfg0 && decoded_req_is_wr) begin // SW write next_c = (field_storage.clmgr_efuse_main_cfg0.ApbOrTdr.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end else if(hwif_in.clmgr_efuse_main_cfg0.ApbOrTdr.we) begin // HW Write - we next_c = hwif_in.clmgr_efuse_main_cfg0.ApbOrTdr.next; load_next_c = '1; end field_combo.clmgr_efuse_main_cfg0.ApbOrTdr.next = next_c; field_combo.clmgr_efuse_main_cfg0.ApbOrTdr.load_next = load_next_c; end

struct { struct { logic next; logic load_next; } ApbOrTdr; } clmgr_efuse_main_cfg0;

struct { struct { logic value; } ApbOrTdr; } clmgr_efuse_main_cfg0;