Error in Umask bits in the ACT_COUNT iMC event on Haswell EP?

[jdmccalpin]

Xeon E5 v3 adds three Umask bits to the ACT_COUNT event (EventSelect 0x05) of the iMC. The current implementation defines Umask 0x11, which does not correspond to the documentation in the Xeon E5 v3 Uncore Performance Monitoring Guide (Intel document 331051-002, June 2015), which defines bit 0 for Reads, bit 1 for Writes, and bit 3 for "Bypass". Reading between the lines, the "Bypass" category appears to be associated with transactions that occur only when the Home Agent to Memory Controller Tracker Queue is empty (e.g., see the description of the BT_CYCLES_NE event in the Home Agent (page 88 of the Uncore Perf Monitoring guide). I did some testing and found that the ACT counts with bits 0&1 set are definitely lower than the ACT counts with bits 3,1,0 set. The difference is slightly over 20% at low utilization (below about 35% of peak DRAM bandwidth), slightly over 10% at 70% bandwidth utilization, and varies between 0% and 6% when operating at over 80% bandwidth utilization. I did not test results with the current setting of bits 4 and 0. The big question in my mind is whether the BYP events are additive with respect to the RD and WR events, or if they are a subset. The description of the BYP event is "Activate due to Write" (same as for the WR event), but the description of the BYPASS_IMC event in the Home Agent says "Only Read Transactions use IMC Bypass". Argh! I could probably build a benchmark that would generate a known number of ACT commands, but it would be a bit of a pain. There are a couple of other BYPASS related events in the HA and IMC that need to be checked -- maybe some more insight can be found there....

[rtevans]

Modified so that bits 3,1,0 aare set. Still unknown if BYP events are addition with respect to the RD and WR events or if they are a subset.