Ventus GPGPU(Verilog Edition)
GPGPU processor supporting RISCV-V extension, developed with Verilog.
Copyright (c) 2023-2024 C*Core Technology Co.,Ltd,Suzhou.
这是“乘影”的Verilog版本，原版（Chisel HDL）链接在这里
乘影开源GPGPU项目网站：opengpgpu.org.cn
目前乘影在硬件设计上还有很多不足，如果您有意愿参与到“乘影”的开发中，欢迎在github上pull request
Architecture
乘影的硬件架构文档在这里
承影的硬件结构框图:
SM核的硬件结构框图:
Getting started
以gassian用例为例，进入testcase/test_gpgpu_axi_top/tc_gaussian:
- 打开
tc.v,选择case的warp数和thread数
在
modules/define/define.v目录下，修改NUM_THREAD，可以更改warp内的thread数量
- 用VCS仿真:
make run-vcs-4w4t- 结果会显示
PASSED或FAILED:
- 用Verdi查看波形
make verdi- 如果不需要对外的AXI接口，则进入
testcase/test_gpgpu_top/tc_gaussian，步骤同上
Case Description
| 测试集 | warp/thread数 | 是否通过 | 说明 |
|---|---|---|---|
| vecadd | 4w16t | pass | 向量加 |
| 4w8t | pass | ||
| 4w32t | pass | ||
| 8w4t | pass | ||
| matadd | 1w16t | pass | 矩阵加 |
| 2w8t | pass | ||
| 4w4t | pass | ||
| nn | 2w16t | pass | 最近邻内插法 |
| 4w8t | pass | ||
| 4w16t | pass | ||
| 8w4t | pass | ||
| 8w8t | pass | ||
| gassian | 1w16t | pass | 高斯消元 |
| 2w8t | pass | ||
| 4w4t | pass | ||
| 4w8t | pass | ||
| bfs | 2w16t | pass | 宽度优先搜索算法 |
| 4w8t | pass | ||
| 4w32t | pass | ||
| 8w4t | pass |
Acknowledgement
We refer to some open-source design when developing Ventus GPGPU.
| Sub module | Source | Detail |
|---|---|---|
| CTA scheduler | MIAOW | Our CTA scheduler module is based on MiaoW ultra-threads dispatcher |
| L2Cache | block-inclusivecache-sifive | Our L2Cache design is inspired by Sifive's block-inclusivecache |
| FPU | XiangShan | We reused Array Multiplier in XiangShan. FPU design is also inspired by XiangShan |
| SFU | openhwgroup | Our SFU module is based on pulp-platform |
| Config, ... | rocket-chip | Some modules are sourced from RocketChip |