Color problem of code block

[zjulijinxin]

When I activate the plug-in, the "begin end" code block changes from multiple colors to only one color

[qarlosalberto]

Can you share the complete code in text?

[zjulijinxin]

Let me show a simple example, the following code:

`module test ( input clk , input rst , output led
);

always @(posedge clk) begin if (rst) begin led <= 0; end else begin led <= 1; end end

endmodule`

When I activate the plug-in（TerosHDL），the "begin end" code block changes from multiple colors to only one color

I think it's due to the conflict between the two plug-ins：TerosHDL and Verilog-HDL/SystemVerilog/Bluespec SystemVerilog

[qarlosalberto]

Yes, it seems a conflict with Verilog-HDL/SystemVerilog/Bluespec SystemVerilog. To check it, can you deactivate Verilog-HDL/SystemVerilog/Bluespec SystemVerilog ?

[qarlosalberto]

And other thing, what extension do you use for the "begin" colors?

[zjulijinxin]

After I deactivate this extension（Verilog-HDL/SystemVerilog/Bluespec SystemVerilog）, the code block has no different color： I use the extension"Verilog HDL / SystemVerilog / bluespec SystemVerilog" to color code blocks.

Plus，I think the coloring function of the extension"Verilog HDL / SystemVerilog / bluespec SystemVerilog" is not easy to use. It would be great if you could develop similar coloring functions.

[qarlosalberto]

It will be fix in the next version.