TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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[Documenter] Member Groups #298

Open le-blue opened 2 years ago

le-blue commented 2 years ago

First of all, thank you for your wonderful toolset! I'd like to suggest a documenter feature:

Feature Request

Background

I like to use packages to specify and document register interfaces, for the embedded system's colleagues that have to deal with my design. At least from my point of view, the grouping feature would increase the Documenter's value for every larger entity / package. In my particular use case, I'm dreaming of a Ref-manual-like register description coming directly from the Documenter.

Related

Might be related to:

qarlosalberto commented 2 years ago

That sounds good. Could you send me and an email to carlosruiznaranjo@gmail.com ?