Don't work Go To Definition with Verilog and SystemVerilog

[WTFive]

Go To Definition work great with VHDL, but don't work with Verilog and SystemVerilog files

• OS: Windows 11
• VSCode version version 1.67.1

The second screenshot shows that this function seems to work, but it does not work correctly. If I have confused something or do not understand and everything is in order, then I apologize in advance

[qarlosalberto]

Does it work fine the "outline"?

[qarlosalberto]

Ok, I see the problem. I will fix it.

[ufktmr]

im having the same problem in win10 vscode version 1.73.1 and terosHDL version v2.0.7

[qarlosalberto]

@ufktmr could you send me an email? carlosruiznaranjo@gmail.com

[alpetrovsky774]

This is still happening in version 5.0 and the pre-release version 6.0. The impact is that autocomplete, go-to definition, hover, and evaluate features do not work for most elements in the Verilog/SV files as those features depend on identification of element names in the file. It does however seem to work fine with VHDL.

For example: input wire [7:0] input_a; // parsed incorrectly, the keyword "wire" is identified as the element name output reg [7:0] output_a; // parsed incorrectly, the keyword "reg" is identified as the element name ... reg [1:0] unsigned_reg; // parsed correctly and name "unsigned_reg" is properly identified reg signed [1:0] signed_reg; // parsed incorrectly, the keyword "signed" is identified as the element name

Based on the above examples it seems that the word following reg/wire or input/output keywords is used as the element name regardless of where the given name is actually located within the line. This prevents autocomplete, go-to definition, hover, and evaluate features from working on most input/output definitions and signed reg/wire definitions.