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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
GNU General Public License v3.0
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Two-dimensional array port export to diagram is abnormal #330

Closed zengzhengqi0524 closed 1 year ago

zengzhengqi0524 commented 2 years ago

The diagram only shows one vector.

qarlosalberto commented 2 years ago

Please, share an reproducible example.

zengzhengqi0524 commented 2 years ago

Please, share an reproducible example. f7bfbfa8-49ef-4458-9e29-668f9f40d23c.png

qarlosalberto commented 2 years ago

Please, share an example in code, not as image.

qarlosalberto commented 2 years ago

In code, not image.

El jue., 21 jul. 2022 10:29, UESTC-ZZQ @.***> escribió:

Please, share an reproducible example.

[image: 8adc121a-4c90-4c37-98f0-d98cdcc6811d.png] https://user-images.githubusercontent.com/50767486/180167913-9799c8d3-64dd-49e6-8d5c-5c8c80d383c9.png

— Reply to this email directly, view it on GitHub https://github.com/TerosTechnology/vscode-terosHDL/issues/330#issuecomment-1191197586, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABNN4RZIAQ2SYXHD5ACC4LTVVEC53ANCNFSM54GHRXOQ . You are receiving this because you commented.Message ID: @.***>

qarlosalberto commented 1 year ago

fixed on v5.0.0