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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
GNU General Public License v3.0
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The highlight for ”ifdef” “else” “endif” “ifndef“ is missing #419

Open beanspower opened 1 year ago

beanspower commented 1 year ago

Hello expert, Describe the bug The hightlight for " ifdef" "else" "endif“ ”ifndef“ are missing.

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I try to modify the "verilog.configuration.json" , but it seems not good enough. Add below codes in brackets image

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beanspower commented 1 year ago

@qarlosalberto Hello Expert ， could you help to check it？

qarlosalberto commented 1 year ago

Please share the code.

beanspower commented 1 year ago

@qarlosalberto Hello expert , I share one example as the code in https://github.com/TerosTechnology/vscode-terosHDL/issues/296 Thanks for your kind help. Example.zip image