search

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
524 stars 42 forks source link

"Maximum call stack size exceeded " while use schematic view #430

Open Devil-SX opened 11 months ago

Devil-SX commented 11 months ago

Describe the bug I want to see my rram module in schematic view. "Schematic view" didn't output an image, while dev tools returned console.ts:137 [Extension Host] stack trace: RangeError: Maximum call stack size exceeded . For other modules, extension worked correctly.

Code The HDL code

module rram #(
    parameter WIDTH = 1152
  ) (
    input clk,
    input rst_n,
    input [WIDTH-1:0] i_data,
    input rw_n,
    input [10:0] i_w_adr,
    input [10:0] i_r_adr,
    output reg [WIDTH-1:0] o_data
  );

  reg [WIDTH-1:0] rram_reg[10:0];

  integer i;
  always @(posedge clk or negedge rst_n)
  begin
    if (!rst_n)
    begin
      for (i = 0; i < 2048; i = i + 1)
      begin
        rram_reg[i] <= 0;
      end
    end
    else
      if (rw_n)
        // Read
      begin
        o_data <= rram_reg[i_r_adr];
      end
      else
        // Write
      begin
        rram_reg[i_w_adr] <= i_data;
      end
  end
endmodule

Output

Vscode output 

2023-07-25 13:07:34.858 [info] D:\Sci\Anaconda\condabin\conda.bat activate teroshdl & yowasp-yosys -p "read_verilog -sv rram.v; ; proc;  ; write_json teroshdl_yosys_output.json; stat"

2023-07-25 13:07:35.223 [info] 
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |

2023-07-25 13:07:35.224 [info]  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.31+13 (git sha1 6965abeef, ccache clang 14.0.0-1ubuntu1 -Os -flto -flto)

-- Running command `read_verilog -sv rram.v; ; proc;  ; write_json teroshdl_yosys_output.json; stat' --

1. Executing Verilog-2005 frontend: rram.v

2023-07-25 13:07:35.303 [info] Parsing SystemVerilog input from `rram.v' to AST representation.
Generating RTLIL representation for module `\rram'.
Warning: Replacing memory \rram_reg with list of registers. See rram.v:22

2023-07-25 13:07:35.907 [info] Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).

2023-07-25 13:07:35.928 [info] Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 3 switch rules as full_case in process $proc$rram.v:16$4 in module rram.
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).

2023-07-25 13:07:35.934 [info] Removed 0 redundant assignments.
Promoted 5 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2023-07-25 13:07:35.934 [info] 
2.5. Executing PROC_ARST pass (detect async resets in processes).

2023-07-25 13:07:36.156 [info] Found async reset \rst_n in `\rram.$proc$rram.v:16$4'.

2.6. Executing PROC_ROM pass (convert switches to ROMs).

2023-07-25 13:07:36.156 [info] Converted 0 switches.
<suppressed ~3 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2023-07-25 13:07:36.313 [info] Creating decoders for process `\rram.$proc$rram.v:16$4'.
     1/22: $3$mem2reg_rd$\rram_reg$rram.v:29$2_DATA[1151:0]$18
     2/22: $2$mem2reg_rd$\rram_reg$rram.v:29$2_DATA[1151:0]$15
     3/22: $2$mem2reg_rd$\rram_reg$rram.v:29$2_ADDR[3:0]$14
     4/22: $2$mem2reg_wr$\rram_reg$rram.v:34$3_DATA[1151:0]$17
     5/22: $2$mem2reg_wr$\rram_reg$rram.v:34$3_ADDR[3:0]$16
     6/22: $1$mem2reg_wr$\rram_reg$rram.v:34$3_DATA[1151:0]$13
     7/22: $1$mem2reg_wr$\rram_reg$rram.v:34$3_ADDR[3:0]$12
     8/22: $1$mem2reg_rd$\rram_reg$rram.v:29$2_DATA[1151:0]$11
     9/22: $1$mem2reg_rd$\rram_reg$rram.v:29$2_ADDR[3:0]$10
    10/22: $1\i[31:0]
    11/22: $0\rram_reg[10][1151:0]
    12/22: $0\rram_reg[9][1151:0]
    13/22: $0\rram_reg[8][1151:0]
    14/22: $0\rram_reg[7][1151:0]
    15/22: $0\rram_reg[6][1151:0]
    16/22: $0\rram_reg[5][1151:0]
    17/22: $0\rram_reg[4][1151:0]
    18/22: $0\rram_reg[3][1151:0]
    19/22: $0\rram_reg[2][1151:0]
    20/22: $0\rram_reg[1][1151:0]
    21/22: $0\rram_reg[0][1151:0]
    22/22: $0\o_data[1151:0]

2023-07-25 13:07:36.314 [info] 
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2023-07-25 13:07:36.329 [info] 
2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2023-07-25 13:07:36.344 [info] Creating register for signal `\rram.\o_data' using process `\rram.$proc$rram.v:16$4'.
  created $dff cell `$procdff$162' with positive edge clock.
Creating register for signal `\rram.\i' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$163' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[0]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$164' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[1]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$165' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[2]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$166' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[3]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$167' with positive edge clock and negative level reset
2023-07-25 13:07:36.357 [info] .
Creating register for signal `\rram.\rram_reg[4]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$168' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[5]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$169' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[6]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$170' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[7]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$171' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[8]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$172' with positive edge clock and negative level reset.
Creating register for signal `\rram.\rram_reg[9]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$173' with positive edge clock
2023-07-25 13:07:36.364 [info]  and negative level reset.
Creating register for signal `\rram.\rram_reg[10]' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$174' with positive edge clock and negative level reset.
Creating register for signal `\rram.$mem2reg_rd$\rram_reg$rram.v:29$2_ADDR' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$175' with positive edge clock and negative level reset.
Creating register for signal `\rram.$mem2reg_rd$\rram_reg$rram.v:29$2_DATA' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$176' with positive edge clock and negative level reset.
Creating register for signal `\rram.$mem2reg_wr$\rram_reg$rram.v:34$3_ADDR' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$177' with positive edge clock and negative level reset.
Creating register for signal `\rram.$mem2reg_wr$\rram_reg$rram.v:34$3_DATA' using process `\rram.$proc$rram.v:16$4'.
  created $adff cell `$procdff$178' with positive edge clock and negative level reset.

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 3 empty switches in `\rram.$proc$rram.v:16$4'.
Removing empty process `rram.$proc$rram.v:16$4'.
Cleaned up 3 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).

2023-07-25 13:07:36.399 [info] Optimizing module rram.
<suppressed ~2 debug messages>

2023-07-25 13:07:36.399 [info] 
3. Executing JSON backend.

2023-07-25 13:07:36.510 [info] 
4. Printing statistics.

2023-07-25 13:07:36.510 [info] 
=== rram ===

   Number of wires:                120
   Number of wire bits:          71625
   Number of public wires:          19
   Number of public wire bits:   15033
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 70
     $adff                          16
     $dff                            1
     $eq                            20
     $logic_not                      3
     $mux                           29
     $pmux                           1

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: d1223485f2, CPU: user 1.29s system 0.00s
Yosys 0.31+13 (git sha1 6965abeef, ccache clang 14.0.0-1ubuntu1 -Os -flto -flto)
Time spent: 53% 2x read_verilog (0 sec), 17% 1x proc_arst (0 sec), ...

Screenshots

image image

Please complete the following information:

qarlosalberto commented 11 months ago

The problem is that the graph is too big. For example it works fine if you change:

    parameter WIDTH = 10

In the version 5.0.7 I have added an alert about this problem.