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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
GNU General Public License v3.0
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Simpler state change conditions in the state machine viewer #437

Open arthurdblrd opened 1 year ago

arthurdblrd commented 1 year ago

When a condition to change state in a state machine is complex, it can make the state machine viewer hard to read and not very explanatory.

It would be great if the user could set the changing condition with a more explanatory text which will appear in the state machine viewer.

Maybe by adding a comment on the line where the new state is set, maybe with a new keyword like @fsmcondition.

qarlosalberto commented 1 year ago

It's a good idea