"HoveringOverSignal, RenameSymbol, Go to.. "not work, when starting vscode and opening vhd-file with errors

[ungultig1]

Hello,

there is a bug I noticed. It's easy to reproduce following these steps:

1. Open your project-Vhdl-file in vscode.
2. put following simple syntax-error: After end of architecture:

architecture rtl of examp is
...
...
.....some vhdl code
...
...
end architecture rtl;

mySignal_out <= signal     --- A nonsense syntax error at end of file

4. Now, TerosHDL still recognizes the signal-declaration and definitions.
5. Now close vsode and open vscode and your project-file again.
6. Result: TerosHDL cannot recognize any signals anymore.

--> Which leads to malfunctions in general for "Rename Symbol" and "Go to Definitions /Declaration" etc.

This issues occur when pasting some pseudo codes in VHDL and working on this. Closing vscode and opening again forces you to make your VHDL-code synthesizable again, before TerosHDL can work again.

Thank you for fixing this issue.

Greetings,

[sravanmohan]

I'm facing the same issue on TerosHDL v5.0.12 with VHDL. While modifying code, there would be unintentional syntax errors which will be fixed eventually during simulation/synthesis. So it would be great if the extension doesn't abruptly stop VHDL code analysis and display.

[qarlosalberto]

This is expected. So I will change the label to enhancement