There is a bug for the documention generator when a parameter is passed that is a data type, which is fully legal SystemVerilog IEEE 1800-2017 code.
For example, the code snippet below will fail to produce all documentation (however state machines are documented) :
module mapping #(
parameter type x_t = type(logic[1:-14]), //! x data type
parameter type y_t = type(logic[7:-24]) //! y data type
)(
input logic clock,
input logic reset,
input logic start,
output logic o_done,
. . . . .
Whereas this code will produce all the documentation with "//! " in the code :
I suspect that one of the auxiliary tools is the problem. I am using Verilator as my parser in TerosHDL, and the code in snippet #1 above Simulates perfectly, so I don't think it is the parser.
There is a bug for the documention generator when a parameter is passed that is a data type, which is fully legal SystemVerilog IEEE 1800-2017 code.
For example, the code snippet below will fail to produce all documentation (however state machines are documented) :
Whereas this code will produce all the documentation with "//! " in the code :
I suspect that one of the auxiliary tools is the problem. I am using Verilator as my parser in TerosHDL, and the code in snippet #1 above Simulates perfectly, so I don't think it is the parser.
Any suggestions appreciated.