Unable to rename elements

[RyzenFromFire]

Describe the bug When in a file opened through TerosHDL's source pane, I cannot rename elements (for instance, entity, architecture, or signal names in VHDL). This does not appear when opening the file normally through VSCode. However, the behavior seems to persist after a file is opened in TerosHDL.

To Reproduce Write any VHDL code with named areas. Example below. Press F2, or right-click and Rename Symbol. A message appears stating "The element can't be renamed."

Code

-- example of code for which various elements cannot be renamed in TerosHDL.
-- the issue is not dependent on the code used.
entity example is
  port (
    input  : in    std_logic_vector(7 downto 0);
    output : out   std_logic
  );
end example;

architecture behavioral of example is

  signal sig : std_logic_vector(7 downto 0);

begin

  sig <= nor input;
  output <= or sig;

end architecture behavioral;

Please complete the following information:

• OS: Windows 10 22H2
• VSCode version information:

  Version: 1.85.1 (user setup)
  Commit: 0ee08df0cf4527e40edc9aa28f4b5bd38bbff2b2
  Date: 2023-12-13T09:49:37.021Z
  Electron: 25.9.7
  ElectronBuildId: 25551756
  Chromium: 114.0.5735.289
  Node.js: 18.15.0
  V8: 11.4.183.29-electron.0
  OS: Windows_NT x64 10.0.19045

  • TerosHDL version: assuming latest release, installed from VSCode marketplace only a few days ago

Screenshots Example of renaming before opening with TerosHDL:

Example of file after opening with TerosHDL:

[qarlosalberto]

It's fixed. Reopen the issue if you have any problem.