TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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Indent Improvement for Verilog/SystemVerilog #569

Open wuch10 opened 5 months ago

wuch10 commented 5 months ago

Could we support the indent rules as the below format? VIM supports it quite well.

always @( posedge iq_rx_clk ) begin if( !jesd_rstn_rxclk ) //auto indent here sysref_cnt <= 'h0; // auto indent here else //auto unindent sysref_cnt <= sysref_cnt + 1; end //auto unindent(twice back-tab)