TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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Documenter: VirtualBus direction not recognized #571

Closed albydnc closed 5 months ago

albydnc commented 5 months ago

Bug description When I specify the direction of the virtual bus using the keyword @dir, the documenter does not recognise it and puts it as a description of the bus.

To Reproduce

entity descrambler is
  port (
    clk_i       : in    std_logic;                                   --! clock
    reset_i     : in    std_logic;                                   --! active high
    --! @virtualbus Avalon-ST sink @dir in
    snk_data_i  : in    std_logic_vector(g_DATA_WIDTH - 1 downto 0); --! data input
    snk_valid_i : in    std_logic;                                   --! input valid signal
    snk_ready_o : out   std_logic;                                   --! ready backpressure to in signal
    --! @end
    --! @virtualbus Avalon-ST source @dir out
    src_valid_o : out   std_logic;                                   --! valid output signal
    src_ready_i : in    std_logic;                                   --! ready backpressure signal
    src_data_o  : out   std_logic_vector(g_DATA_WIDTH - 1 downto 0)  --! data output
  --! @end
  );
end entity descrambler;

Please complete the following information:

Screenshots image

qarlosalberto commented 5 months ago

The description should be at the end:

    --! @virtualbus Avalon-ST @dir in sink
albydnc commented 5 months ago

Thank you, this solved the issue.