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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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The outline does not work well. #583

Open narutozxp opened 4 months ago

narutozxp commented 4 months ago

The window of outline does not show the correct port signal but shows the type of signal. Just as follows. N_0EI``2H8C@E78KECJ}H O

OS: win10 VSCODE: 1.86.2 TerosHDL:5.0.12