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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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FSM image generator doesn't support conditional operator ( ? ). #588

Open tms4517 opened 3 months ago

tms4517 commented 3 months ago

Describe the bug The conditional operator is not supported. For an image to be generated, replace ?, with if else statements.

To Reproduce See diff: https://github.com/tms4517/Yosys_to_aid_with_RTL_design/commit/57cfb14fc4e5f5aef2e1236bc8f05f0a9d4fe48f

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