FSM image generator requires `begin` and `end`.

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

https://terostechnology.github.io/terosHDLdoc/

524 stars 42 forks source link

Open tms4517 opened 3 months ago

tms4517 commented 3 months ago

Describe the bug Begin and end keywords are required to be enclosed around always_comb process blocks for an image to be generated.

To Reproduce See diff: https://github.com/tms4517/Yosys_to_aid_with_RTL_design/commit/5bc1960aa5e5cca50ef6a6118e27ffb84f7c490f

Screenshots Without:

With: