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TerosTechnology / vscode-terosHDL

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Added type record parsing and table creation. #599

Closed gmartina closed 2 months ago

gmartina commented 2 months ago

I am working on this bugfix #595 . Record table creation is finished. Next step is type enum.

@qarlosalberto do you like this format?

image

qarlosalberto commented 2 months ago

good job! Yes, I like

qarlosalberto commented 2 months ago

It could really nice if you can expand the tests.

gmartina commented 2 months ago

PR updated. Output example:

Entity: entity_dummy

Diagram

Diagram

Ports

Port name Direction Type Description
clk in std_logic Clk description...
reset in std_logic Reset description...

Types

Name Type Description
my_custom_type0 range 0 to 1000 0my type comment
my_custom_type1 range -5 to 5 1my type comment
my_custom_type2 range -1000 to 5000 2my type comment

Records

sample_record1

Sample record type 1 Name Type Description
single_bit std_logic Comment single_bit
byte_data std_logic_vector (7 downto 0) comment byte_data

sample_record2

Sample record type 2

Name Type Description
single_bit std_logic Comment single_bit
byte_data std_logic_vector (7 downto 0) comment byte_data
byte_data std_logic_vector (7 downto 0) comment byte_data
byte_data std_logic_vector (7 downto 0) comment byte_data

Enums

t_fsm1

My FSM...

Name Description
FSM1 FSM1 comment...
FSM2 FSM2 comment...
FSM3 FSM3 comment...

t_fsm2

My FSM 2...

Name Description
FSM_A FSM_A comment...
FSM_B FSM_B comment...
FSM_C FSM_C comment... 

library ieee;
  use ieee.std_logic_1164.all;

entity entity_dummy is
    port (
        clk   : in std_logic; --! Clk description...
        reset : in std_logic; --! Reset description...

    );
end entity;

architecture rtl of entity_dummy is

    --! Sample record type 1
    type sample_record1 is record
        single_bit : std_logic; --! Comment single_bit
        byte_data : std_logic_vector (7 downto 0); --! comment byte_data
    end record sample_record;

    --! Sample record type 2
    type sample_record2 is record
        single_bit : std_logic; --! Comment single_bit
        byte_data : std_logic_vector (7 downto 0); --! comment byte_data
        byte_data : std_logic_vector (7 downto 0); --! comment byte_data
        byte_data : std_logic_vector (7 downto 0); --! comment byte_data
    end record sample_record;

    --! My FSM...
    type t_fsm1 is (FSM1, --! FSM1 comment...
        FSM2, --! FSM2 comment...
        FSM3 --! FSM3 comment...
        );

    --! My FSM 2...
    type t_fsm2 is (FSM_A, --! FSM_A comment...
    FSM_B, --! FSM_B comment...
    FSM_C --! FSM_C comment...
    );

    --! My tipe
    type my_custom_type0 is range 0 to 1000; --! 0my type comment
    type my_custom_type1 is range -5 to 5; --! 1my type comment
    type my_custom_type2 is range -1000 to 5000; --! 2my type comment

begin

end architecture;
gmartina commented 2 months ago

It could really nice if you can expand the tests.

I may need some help with that. where should i add the test for this?

gmartina commented 2 months ago

@qarlosalberto Ready for review.

qarlosalberto commented 2 months ago

nice!!