Describe the bug
If there's a generic that has a string "PORT" in the identifier (e.g. "PORT_COUNT"), running the VHDL formatter with Standalone formatter breaks the file
To Reproduce
Format the following minimal VHDL entity in editor:
entity my_ent is
generic (PORT_COUNT : natural);
port(port_ena : bit_vector(PORT_COUNT-1 downto 0));
end entity;
Right click on file and click "Format document" or SHIFT + ALT + F
Expected to have nice formatting, but seems like the port inside a generic name (which should be completely fine!) breaks the formatting and gives a following "formatted" document as output, breaking the VHDL syntax completely.
entity my_ent is
generic
(
port
_COUNT : natural);
port
(
port_ena : bit_vector(port
_COUNT - 1 downto 0));
end entity;
Seems like the problem is if the generic starts with "PORT". E.g. "COUNT_PORT" does not trigger this error
Describe the bug If there's a generic that has a string "PORT" in the identifier (e.g. "PORT_COUNT"), running the VHDL formatter with Standalone formatter breaks the file
To Reproduce Format the following minimal VHDL entity in editor:
Right click on file and click "Format document" or SHIFT + ALT + F
Expected to have nice formatting, but seems like the port inside a generic name (which should be completely fine!) breaks the formatting and gives a following "formatted" document as output, breaking the VHDL syntax completely.
Seems like the problem is if the generic starts with "PORT". E.g. "COUNT_PORT" does not trigger this error
Environment information: