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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
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Fix unwanted formating when generic and/or port names contain "generic" or "port" keywords. #604

Closed gmartina closed 2 months ago

gmartina commented 2 months ago

602 Fix unwanted formating when generic and/or port names contain "generic" or "port" keywords.

qarlosalberto commented 2 months ago

thanks for that!