TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
524 stars 42 forks source link

Formatter rules enforcing #619

Open knyfi opened 1 month ago

knyfi commented 1 month ago

Formatter using VSG does not enforce prefix and suffix rules :

To Reproduce

rule file contains :

rule:
  constant_015:
    disable: false
    prefixes: ['CST_']

vhdl file contains : constant FAULTY_CONSTANT: std_logic_vector(7 downto 0) := x"AA";

Observation: The formatter does not add prefix to constant.

Please complete the following information:

qarlosalberto commented 1 month ago

Some questions:

  1. Make sure that you have the same configuration in "formatter and "linter". You have to put the same rules path in both places.
  2. Can you try to define other rules. Does it work?
knyfi commented 1 month ago

@qarlosalberto

Hello,

I just tried adding the ruleset to the linter but nothing changed. Other rules (case rules mostly) do get checked and corrected.

qarlosalberto commented 1 month ago

Then it seems a problem in VSG. I think that not all the rules are self-solvable by the formatter.

knyfi commented 1 month ago

Well it would seem that VSG does detect the violation but the formatter doesn't correct it. perhaps this would be feature request more than a bug then.

qarlosalberto commented 1 month ago

You can try to run VSG manually. If it doesn't work, then it's an issue for VSG repo.