Schematic viewer dosen't work

[deleteTh]

TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)! When I'm in the CMD window input yowasp-yosys -p 'read_verilog axis_async_fifo.v;' , CMD window output : /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf claire@yosyshq.com | | Distributed under an ISC-like license, type "license" to see terms | ----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, ccache clang 14.0.0-1ubuntu1.1 -Os -flto -flto)

-- Running command `read_verilog axis_async_fifo.v;' --

1. Executing Verilog-2005 frontend: axis_async_fifo.v Parsing Verilog input from axis_async_fifo.v' to AST representation. Generating RTLIL representation for module\axis_async_fifo'. Warning: Replacing memory \m_axis_pipe_reg with list of registers. See axis_async_fifo.v:658 Successfully finished Verilog frontend.

Warnings: 1 unique messages, 1 total End of script. Logfile hash: b21028a549, CPU: user 0.05s system 0.00s Yosys 0.42 (git sha1 9b6afcf3f, ccache clang 14.0.0-1ubuntu1.1 -Os -flto -flto) Time spent: 100% 2x read_verilog (0 sec)

Configure environment:

• OS: win10
• VSCode version:1.90.0
• teroshdl version:v6.0.1
• python version:3.12.0rc3

1. "yowasp-yosys --help" can in CMD and Power Shell work.

2. In CMD window use "make --version" output: GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

This program built for i386-pc-mingw32

3. My environment variable configure: D:\devSoft\Python\Python312\Scripts\ D:\devSoft\Python\Python312\ C:\Windows\System32

4. In schematic viewer: General >> Select the backend >> YoWASP(Only Verilog/SV), other configurations remain by default.

[qarlosalberto]

Can you share an example to reproduce it?

El mié., 19 jun. 2024 4:21, deleteTh @.***> escribió:

TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)!

Configure environment:

• OS: win10
• VSCode version:1.90.0
• teroshdl version:v6.0.1
• python version:3.12.0rc3

• 1.

  "yowasp-yosys --help" can in CMD and Power Shell work. 2.

  In CMD window use "make --version" output: GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

This program built for i386-pc-mingw32

3.

My environment variable configure: D:\devSoft\Python\Python312\Scripts D:\devSoft\Python\Python312 C:\Windows\System32 4.

In schematic viewer: General >> Select the backend >> YoWASP(Only Verilog/SV), other configurations remain by default.

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[deleteTh]

axis_async_fifo.txt

[deleteTh]

I found that many verilog file cannot be generated.

[qarlosalberto]

Could you try with this version? https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/latest I have added more log. Yo should see on top the current command:

Share it here, so I can see the problem.

[deleteTh]

[deleteTh]

ErrorInfo.txt

[deleteTh]

When I use this command : yowasp-yosys -p 'read_verilog -sv d:/workSpace/sim/fifo/axis_async_fifo.v; ; hierarchy -top axis_async_fifo; proc; ; write_json C:/Users/LBWB_WT/.teroshdl_0hHab; stat', then CMD window was no error.