TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
GNU General Public License v3.0
542 stars 45 forks source link

Feature: Format selection #625

Open ckuhlmann opened 3 months ago

ckuhlmann commented 3 months ago

Is your feature request related to a problem? Please describe. Formatting a complete document might interfere with some custom (but useful) formatting. Auto-formatting individual sections would still be very helpful.

Describe the solution you'd like Select part of a VHDL or Verilog or SV file and have "Format selection" ("editor.action.formatSelection", when EditorHasDocumentSelectionFormattingProvider) available in VSCode. Teros will then apply formatting only to the selected lines and will leave the rest of the document untouched.

Describe alternatives you've considered Manually aligning := and <= is very tedious, but messing up an otherwise carefully formatted file with a full format is also tedious...

Additional context For simplicity, it can be assumed that only whole blocks / nesting levels will be selected, i.e. no "begin ..." without "end ...;", "(" without ")", etc. will be selected. If the selection formatter is used in a case where only part of a sub-level is selected, it may either ignore the request or produce sub-optimal / incomplete formatting.