The ability to import packages is an important SystemVerilog feature. I use packages in all my designs. The import syntax seems to be understood but it is reported that it can't find the package, but it's in my project. Subsequently, any parameters/functions/symbols defined in my packages show up as errors (undefined variables). Can you please support this feature?
The ability to import packages is an important SystemVerilog feature. I use packages in all my designs. The import syntax seems to be understood but it is reported that it can't find the package, but it's in my project. Subsequently, any parameters/functions/symbols defined in my packages show up as errors (undefined variables). Can you please support this feature?