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TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://terostechnology.github.io/terosHDLdoc/
GNU General Public License v3.0
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verilog testbench #629

Closed deleteTh closed 4 weeks ago

deleteTh commented 3 months ago

2 axis_async_fifo_tb.txt axis_async_fifo.txt

qarlosalberto commented 3 months ago

Please, add more details.

deleteTh commented 3 months ago

When I use TerosHDL:Generate template >> Verilog testbench, then (wire wire) or (reg wire) will appear before some signal names. There will be grammatical errors.

qarlosalberto commented 4 weeks ago

Issue resolved. Please feel free to reopen the case if the problem persists.