verilog snippets error - Githubissues

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

https://terostechnology.github.io/terosHDLdoc/

524 stars 42 forks source link

verilog snippets error #632

Open narutozxp opened 3 days ago

narutozxp commented 3 days ago

Describe the bug https://github.com/TerosTechnology/vscode-terosHDL/blob/81d4c80f541ef7af6f06d046f1230a3ecdc6c4b1/packages/teroshdl/snippets/verilog/verilog.json#L105-L110

the following is correct

"define": {
"prefix": "def",
"body": [
    "`define $1 = $2"
],
"description": "`define var = val"
},