VHDL comment type for Verilog testbench template - Githubissues

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

https://terostechnology.github.io/terosHDLdoc/

GNU General Public License v3.0

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VHDL comment type for Verilog testbench template #656

Open SebekO opened 2 months ago

SebekO commented 2 months ago

Describe the bug If you define your own configurable header under Templates: General and create Verilog testbench template, it will generate VHDL comments style for it.

To Reproduce Create Verilog testbench template with own configurable header.

Code You can use this example like your configurable header:

Company: XXX
Engineer: XXX
Create Date: XX/XX/XXXX
Design Name: XXX
Module Name: XXX
Project Name: XXX
Target Devices: RFSoC
Tool Versions: 2023.1
Description: XXX
Dependencies:
Revision:
Revision 0.01 - File Created
Additional Comments:

Please complete the following information:

OS: Ubuntu 20.04
VSCode 1.92.2

Screenshots

Additional context I found previous bug but with opposite problem: https://github.com/TerosTechnology/vscode-terosHDL/issues/465