Tsai-Cheng-Hong / Verilog-ADPLL

ADPLL 完成階段:Synthesis
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Can you provide further information about the *.sp file? #1

Closed wxknxxzj closed 2 years ago

wxknxxzj commented 2 years ago

Hi! I successfully run the *.v code, thank you for sharing. I would like your support for the following:

  1. I learned that some .v codes can't be synthesized, but it's not a big problem. If I want to continue to use .sp files for simulation, how to do it? Is there a missing file for some simulation support?
  2. Can you provide a reference article for the code? The code is not easy to understand. Looking forward to your reply and I will continue your work.

嗨,您好!我成功的运行了*.v的代码,很感谢您的分享。我想得到您的以下支持:

  1. 我了解到部分.v代码貌似不能综合,但问题不大。如果我想继续使用.sp文件来仿真,如何进行呢?是不是缺少了部分模拟支持的文件呢?
  2. 能否提供代码的参考文章呢? 困难于代码的理解。

期待您的回复,我将继续您的工作。

Tsai-Cheng-Hong commented 2 years ago

Hi! I successfully run the *.v code, thank you for sharing. I would like your support for the following:

  1. I learned that some .v codes can't be synthesized, but it's not a big problem. If I want to continue to use .sp files for simulation, how to do it? Is there a missing file for some simulation support?
  2. Can you provide a reference article for the code? The code is not easy to understand. Looking forward to your reply and I will continue your work.

嗨,您好!我成功的运行了*.v的代码,很感谢您的分享。我想得到您的以下支持:

  1. 我了解到部分.v代码貌似不能综合,但问题不大。如果我想继续使用.sp文件来仿真,如何进行呢?是不是缺少了部分模拟支持的文件呢?
  2. 能否提供代码的参考文章呢? 困难于代码的理解。

期待您的回复,我将继续您的工作。

1.合成的部分我是使用Ultrasim來模擬,因為.sp的寫法是使用Spice的寫法 至於能不能使用合成軟體進行合成,這部分我也沒有測試過 模擬的部分需要Virtuoso ultrasim將PFD、Controller、DCO、FREQ_Div匯入即可。

  1. Code沒有參考文章,均為自己想的

  2. I use Ultrasim to simulate the synthesis, because the writing method of .sp is the writing method of Spice As for whether it can be synthesized using synthesis software, I have not tested it. The simulation requires Virtuoso ultrasim to import PFD, Controller, DCO, and FREQ_Div.

  3. There are no reference articles in Code, they are all their own thoughts

wxknxxzj commented 2 years ago

好的,感谢您的解答。