Verilog-ADPLL
Lab04b (DCO&PFD) & Lab04c (Controller) 是Verilog
Lab05b (DCO) & Lab05d (PFD) 是Hspice
延伸閱讀 Read-Around
Verilog-base
20180327 - Half Adder & Full Sub、Multiplier
20180403 - Assign Adder & Assign Multiplier & 2-1 Multiplexer & 1-4 Multiplexer & Full Adder
20180410 - if-else & case
20180417 - 2's complement & 1-4 、 4-1 Mulplexer
20180508 - up counter & down counter & trigger counter
20180515 - SISO & SIPO
20180522 - Divider-10 & Ring counter
20180529 - Divider & PWM-40% Duty Cycle & PWM-70% Duty Cycle &
20180605 - Detector
20180612 - Detector & x^7+x^3+x+1 & Marquee
https://github.com/Tsai-Cheng-Hong/Verilog-Basic
Verilog-Normal:
OR & NOR gate-Layout & schematic
RPA & CLA-Spice
Shortest Path Faster Algorithm (SPFA)-Verilog
Square root-Verilog
https://github.com/Tsai-Cheng-Hong/Verilog-Normal
Verilog-Advanced:
4-bits Booth Multiplier (4bits布斯乘法器)
Skyline
Incenter of a Triangle
Kmeans Clustering Algorithm
https://github.com/Tsai-Cheng-Hong/Verilog-Advanced
IEEE 754 Standard(64-bits Floating point multiplication)
完成階段:Post-Layout
Verilog-ADPLL
完成階段:Synthesis
https://github.com/Tsai-Cheng-Hong/Verilog-ADPLL
Verilog-TSRI(CIC)-Lab
Lab01-FA
Lab02-MUX
Lab03-ALU
Lab04-Modeling Delay
Lab05-Testbench of ALU
Lab06-Memory
Lab07-FSM
Lab08-Sequence Controller
https://github.com/Tsai-Cheng-Hong/Verilog-TSRI_Lab
FPGA-Based-System-Design
專題1自動上下數 Auto Counter
專題2手動上下數 Switch Counter
專題3霹靂燈 Marquee
專題4移動蛇 Snake Light
專題5紅綠燈 Traffic Light
專題6亂數產生器 Random
專題7密碼鎖 Combination Lock
專題8電子琴 Buzzer
專題9萬年曆 Perpetual Calendar
https://github.com/Tsai-Cheng-Hong/FPGA-Based-System-Design
Transmission-System-Circuit-Design-and-Simulation
E2Frame Format
DS3 Signal Format G.752
https://github.com/Tsai-Cheng-Hong/Transmission-System-Circuit-Design-and-Simulation
Communication-Network-Integrated-Circuit-Design
https://github.com/Tsai-Cheng-Hong/Communication-Network-Integrated-Circuit-Design
Undergraduate senior project : PWM-power-Regulator-smart-air-purifier
