Potential scheduling issue for inter-task dependency loop

[Licheng-Guo]

If task A writes data to task B, then task B writes data to task A. Task A will have patterns like:

fifo_A_to_B.write(); fifo_B_to_A.read();

This will cause a deadlock if the two operations are scheduled into the same cycle. We may need some static analysis to check for this situation and insert ap_wait() to break them.

[linghaosong]

I think add a return bool value to blocking write can also resolve this issue. Currently blocking write is a void function.

[Blaok]

Did some experiments. It seems that Vitis HLS has the same problem. It's probably practically more useful to integrate the FLASH simulator than pinning our hope to static analysis.

#include <hls_stream.h>

void Foo(hls::stream<float>& x, hls::stream<float>& y, hls::stream<float>& a) {
  for (;;) {
    x.write(1.0f);
    a.write(y.read());
  }
}

void Bar(hls::stream<float>& b, hls::stream<float>& x, hls::stream<float>& y) {
  for (;;) {
    y.write(b.read() + x.read());
  }
}

void Top(hls::stream<float>& a, hls::stream<float>& b) {
  hls::stream<float, 32> x, y;
#pragma HLS dataflow
  Foo(x, y, a);
  Bar(b, x, y);
}

yielded

[HLS 200-10] ----------------------------------------------------------------
[HLS 200-42] -- Implementing module 'Foo'
[HLS 200-10] ----------------------------------------------------------------
[SCHED 204-11] Starting scheduling ...
[SCHED 204-61] Pipelining loop 'VITIS_LOOP_5_1'.
[HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'VITIS_LOOP_5_1'

This would lead to a deadlock since y won't be available unless x has been written.

@yk-choi-yk FYI we talked about this earlier; Vitis HLS does not handle complicated dataflow either :)