TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
TAPA explicitly decouples communication and computation for better QoR.
TAPA integrates the AutoBridge floorplanner to optimize the RTL generation process.
TAPA achieves 2× higher the frequency on average compared to Vivado. 1
TAPA compiles 7× faster than Vitis HLS. 2
TAPA provides 3× faster software simulation than Vitis HLS.2
TAPA provides 8× faster RTL simulation than Vitis.
[in-progress] TAPA is integrating RapidStream that is up to 10× faster than Vivado.3
TAPA extends the Vitis HLS syntax for richer expressiveness at the C++ level.
TAPA provides dedicated APIs for arbitrary external memory access patterns.
TAPA allows users to explicitly specify parallelism.
In addition to static burst analysis, TAPA supports runtime burst detectuion by transparently merging small memory transactions into large bursts.
TAPA significantly reduce the area overhead of HBM interface IPs compared to Vitis HLS.
TAPA includes an automated design space exploration tool to balance the resource pressure and the wire pressure for HBM FPGAs.
TAPA automatically select the physical channel for each top-level argument of your accelerator.