Cannot find <ap_int>

[tangyuelm]

Hello, I want to use autobridge on U280. I tried your bandwidth example in the folder /tapa/apps/bandwidth, since I want to achieve 512 bits data transmission. /tapa/apps/bandwidth. However, it reports the error as "lfsr.h:4:10: fatal error: ap_int.h: No such file or directory" with only software simulation. I tried Vitis 2021.2 and 2020.2 but both failed. Could you take a look of it?

Besides, it seems that autobridge only supports U250 and U280. Is there an updated version to support other boards like U200?

Best Wishes, Yue

[tangyuelm]

Besides, I found that AutoBridge made lots of optimization in FIFO. However, my design highly relies on BRAM for data reuse. Can this tool also work well for BRAMs? If so, do I also need to define the array partition and array core type, or it can optimize based on my logic?

[tangyuelm]

The problem is solved after adding some path. However, when I do synthesis on U280, it seems that the tool cannot work for the DDR connection.

[Blaok]

Besides, I found that AutoBridge made lots of optimization in FIFO. However, my design highly relies on BRAM for data reuse. Can this tool also work well for BRAMs?

I think @moazin and @Licheng-Guo are working on a solution. It is harder to make AutoBridge work for BRAMs because they are generally not latency-insensitive; we cannot arbitrarily insert registers without breaking correctness. What we can do is to rerun HLS with an increased BRAM latency after initial floorplanning.

If so, do I also need to define the array partition and array core type, or it can optimize based on my logic?

@moazin This is something worth considering. Users might want to customize not only the array partition, but also the core type.

problem is solved after adding some path. However, when I do synthesis on U280, it seems that the tool cannot work for the DDR connection.

U280 does not have a DDR[2] or DDR[3] since it only has 2 DDR channels. Can you replace DDR with HBM and try again?

[moazin]

@Blaok By core type we mean BRAM/URAM, right? Just yesterday I've been playing with the core type in one of the examples that I'm working on.

[AriesLL]

@tangyuelm when you mean array core type, what is that?

[tangyuelm]

Thanks for your reply. The bandwidth example can work when using HBM. When I say core type, I mean if it is RAM_S2P_BRAM, RAM_T2P_BRAM, etc. For example, when I want to use a BRAM, I need to specify some characteristics as follows. static float a[4][1024];

pragma HLS RESOURCE variable=a core=RAM_S2P_BRAM

pragma HLS ARRAY_PARTITION variable=a complete dim=1

Does tapa has some APIs to specify these characteristics, or it will automatically specify with only declaring the array, or it requires to write the above original HLS APIs?

[Licheng-Guo]

Please take a look at our documents and example designs. You could write any pragma is inside a task.

On Thu, Sep 8, 2022 at 6:27 AM tangyuelm @.***> wrote:

Thanks for your reply. The bandwidth example can work when using HBM. When I say core type, I mean if it is RAM_S2P_BRAM, RAM_T2P_BRAM, etc. For example, when I want to use a BRAM, I need to specify some characteristics as follows. static float a[4][1024];

pragma HLS RESOURCE variable=a core=RAM_S2P_BRAM

pragma HLS ARRAY_PARTITION variable=a complete dim=1

Does tapa has some APIs to specify these characteristics, or it will automatically specify with only declaring the array, or it requires to write the above original HLS APIs?

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