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UCLA-VAST / tapa

TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
https://tapa.rtfd.io
MIT License
144 stars 27 forks source link

How to add RTL blackbox #145

Open logosAllen opened 6 months ago

logosAllen commented 6 months ago

Hi all,

Is there any way to add my RTL blackbox into TAPA project? Since some blocks are more suitable in RTL. Thanks.

Blaok commented 6 months ago

Hi @logosAllen,

It is indeed possible, although the process is somewhat manual. Let me explain with the vadd example, which is usually compiled into .xo as follows:

tapa --work-dir /home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo.tapa \
  analyze -f /home/ubuntu/tapa/apps/vadd/vadd.cpp --top VecAdd \
  synth --platform xilinx_u250_gen3x16_xdma_4_1_202210_1 \
  link \
  pack --output /home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo

To add an RTL blackbox, you'll still want to provide an HLS implementation so that csim can work. The body of the fake implementation can be #ifdef __SYNTHESIS__ protected so that you don't have to make it synthesizable. HLS will still generate proper interfaces so that your RTL blackbox can match those interfaces. To inject the RTL blackbox, you'll need to break the above single CLI command into two parts.

First, run steps up to HLS so that the RTL files are generated:

tapa --work-dir /home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo.tapa \
  analyze -f /home/ubuntu/tapa/apps/vadd/vadd.cpp --top VecAdd \
  synth --platform xilinx_u250_gen3x16_xdma_4_1_202210_1 \
  link

You can then replace the RTL files under hdl of the work directory (/home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo.tapa/hdl in the example).

Finally, pack the RTL files:

tapa --work-dir /home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo.tapa \
  pack --output /home/ubuntu/tapa/build/Debug/apps/vadd/VecAdd.xilinx_u250_gen3x16_xdma_4_1_202210_1.hw.xo

Note that Vivado does not seem to do any checking when packing .xo; no error will be reported until you run RTL simulation, if there are syntax errors in your RTL file.

You might want to leverage to TAPA's fast RTL simulation feature to iterate quickly.