Other RLT simulator Compilation Errors in top_name.v, relay_station.v, and async_mmap.v Due to Undeclared Parameters and Variables

[logosAllen]

In the generated files top_name.v and relay_station.v, there are several I/O ports with parameter bit-widths that have not been declared. This omission causes compilation errors in other RTL simulators.

Additionally, in async_mmap.v, the variable write_data_empty_n is used before its declaration, which also leads to a compilation error in RTL simulators.

Could the authors of TAPA address these issues? Thank you for your assistance.

[Blaok]

Hi @logosAllen,

How do I reproduce the simulator errors? I do run iverilog on the Verilog files and it's not reporting errors.

[logosAllen]

Hi @Blaok ,

I use VCS.

Errors come from:

relay_station.v: https://github.com/UCLA-VAST/tapa/blob/4847fa5d6d0c14d0a7872059c2a8632bafedec6c/backend/python/tapa/assets/verilog/relay_station.v#L246-L270

async_mmap.v: https://github.com/UCLA-VAST/tapa/blob/4847fa5d6d0c14d0a7872059c2a8632bafedec6c/backend/python/tapa/assets/verilog/async_mmap.v#L295-L301

[Blaok]

I don't have access to VCS, but c57b3a38449f28079d690d488f9d22ffa4fc8c5d should fix this. Feel free to reopen if not. Thanks for the detailed report!

[logosAllen]

Hi @Blaok ,

I left out this module, it has the same issue. https://github.com/UCLA-VAST/tapa/blob/84fc3d043bb0391b100d683947552a600daf5467/backend/python/tapa/assets/verilog/relay_station.v#L335-L345 Thank.

[logosAllen]

Hi @Blaok,

Also, there are some port bit mismatch in synthesized [top kernel name].v file. The m_axi_XX_ARLOCK and m_axi_XX_AWLOCK are one bit. But the m_axi_XX_ARLOCK and m_axi_XX_AWLOCK of sub modules are two bit.

Thanks.

[Blaok]

I left out this module, it has the same issue.

https://github.com/UCLA-VAST/tapa/blob/84fc3d043bb0391b100d683947552a600daf5467/backend/python/tapa/assets/verilog/relay_station.v#L335-L345

Thanks, fixed in 60cc41ce7580ce2578f7d78ba8ab5b0b0fe1a034.

Also, there are some port bit mismatch in synthesized [top kernel name].v file. The m_axi_XX_ARLOCK and m_axi_XX_AWLOCK are one bit. But the m_axi_XX_ARLOCK and m_axi_XX_AWLOCK of sub modules are two bit.

This unfortunately cannot be fixed because it is an HLS bug. According to ARM's official documentation, AxLock is supposed to be a single 1-bit for AXI4, but HLS generates 2 bits. Only AXI4 supports 8-bit AxLEN; TAPA just has to throw away the 1 extra bit from AxLOCK.