DRC Rules For GRAMM - Githubissues

The following are the DRC rules checks we are going to incorporate in GRAMM. Please add to this list when more DRC checks are thought of and needed

Device Model DRC

[x] Input pins must only have one fanout edge
[x] Output pins must only have one fanin edge
[x] FuncCells must have input and output pins before the functional unit (PE/Memport)
[x] Device model graph must not have a floating node
[x] I/O and LS ports must have one input and one output pin
[x] Check if there is a routing path between each FuncCell
[x] Check if the G_Name, G_NodeCell, and G_NodeType attributes for the device model graph (Mandatory for device model graph)
[x] Check if the G_VisualX, and G_VisualY attributes for the device model graph (Optional for device model graph)

Application Graph DRC

[x] Application graph must not have a floating node
[x] Functional Unit opcode and pragmas in DRC (Will not be supported in the DRC)
[x] Must not have an unknown pin labelled on the edges
[x] Check if the name, opcode, loadPin, and driverPin attributes for the application DFG (Mandatory for application DFG)
[x] Check if the latency, placementX, and placementY attributes for the application DFG (Optional for application DFG)

UniversalGRAMM / UGRAMM