Irregular reads from DMA

[stv0g]

In GitLab by @hatimak on Jul 8, 2020, 13:19

DMA reads are irregular, sometime they are out of sequence or sometime more there is an additional read (for example, if 2 packets are sent per frame, sometime the DMA reads 3 packets). [Skype call, 07 July 2020]

Another interesting irregularity is that DMA reads "old" data even when the RSCAD simulation is not running. More precisely, an RSCAD simulation was running and sending data to Aurora, then the simulation was turned off and villas-fpga-pipe was exit via Ctrl-C, then villas-fpga-pipe was started again (but not the RSCAD simulation), and then the program read the "stale" data from the last run. Although it read only the last few frames from the "stale" run. [Further testing, 08 July 2020]

[stv0g]

Thats an interesting behaviour. I cant really explain where the stale data is buffered.

Do you see only a single AXI-Stream Frame of old data? Or multiple frames?

Maybe we did not properly clear some of the status flag of the DMA and therefore we always assume that a new DMA transaction has been competed even if it still pending...

I have to check again, how we use the interrupts of the DMA to sync the completions of DMA transactions. We had multiple options for this in the past:

• Polling status register of DMA IP
• Use Message Signalled Interrupts (MSI)
• Poll status register of Interupt Controller (INTC) on the FPGA board..

We can find more about it in the ips/intc.c file

[stv0g]

In GitLab by @hatimak on Jul 10, 2020, 13:39

I see multiple frames of the old data, although not all of it. I wanted to run it again and post an output, but I will do that as soon as Ernie has the new RT kernel :)