This directory contains HDL projects for Virtex 5 (ML507) / Virtex 6 (ML605) based FPGA evaluation boards which can be used to exchange sample values with an RTDS simulator.
xsg
Xilinx System Generator filesips
rtds_axis
An AXI4-Stream to RTDS_InterfaceModule interfaceaxi_pcie_intc
New PCI-MSI interrupt controller (embeds AXI interrupt controller)pcie_msi_requester
Previous PCI-MSI interrupt controllerhdl_multiply
An AXI4-Stream floating point multiplier implemented in VHDLhls_multiply
An AXI4-Stream floating point multiplier implemented in HLShls_decimate
An AXI4-Stream decimation / downsamplerhls_dft
An AXI4-Stream discrete fourier transformationibufds_gte2
A GTE2 IBUFDS block for Xilinx IP integratorrscad
Some example RSCAD drafts to test the S2SS <-> RTDS interface.vc707
Xilinx VC707 Virtex 7 Evaluation Board
vc707_pcie
vc707_villas
vc707_villas_simple
vc707_prom_flasher
aurora_rtds
Vivado project for Aurora <-> RTDS link with VC7072017-2019, Institute for Automation of Complex Power Systems, EONERC
This project is released under the terms of the GPL version 3.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
For other licensing options please consult Prof. Antonello Monti.
Institute for Automation of Complex Power Systems (ACS) EON Energy Research Center (EONERC) RWTH University Aachen, Germany