Generated code is wrong

[solmersa]

The generated code has square brackets instead of curly brackets for vector and also lacks comma as separator, it is separated by spaces instead.

tim::vx::Quantization convolution_16_bias_quant(tim::vx::QuantType::NONE, [6.0480506e-05 2.0013793e-04 5.6733566e-05], 0);

[lileiigithub]

Thanks for your feedback, it's weird that the tim::vx::QuantType::NONE symbol appears which means failed quantization. And could you please provide your ut model and Acuitylite quantization code for us to reproduce this issue?

Thanks.

[solmersa]

Hi, thanks for your quick reply. The model is a TFLite 2.0 quantized model, according to the AcuityLite docs that model does not need further quantization with AcuityLite.

As it is a TFLite 2.6.0 model it is quantized by default using INT8 data types, is INT8 supported by TIM-VX or only UINT8? SDK Docs seems to suggest both are supported.

Here is attached the conversion script.

Model-Conversion.zip

[lileiigithub]

Acuitylite quantization/exporter only supports aymu8 (UINT8 for tflite model) now, and we'll support perchanneli8(INT8 for tflite model) quantization/exporter and other features next version. We'll release the next version this month or next month. Thanks.

[lileiigithub]

BTW, you can use vx-delegate to export the app running on TIM-VX. Refs: https://github.com/VeriSilicon/tflite-vx-delegate Thanks.

[solmersa]

Thanks for this tip, that sounds interesting.
Does TIM-VX support quantized INT8 tfLite model thru the tflite-vx-delegate?, that would be great!. There is some confusion in the forums about TIM-VX supporting or not INT8 Quantization. BTW I am targeting the A311D chip.

[lileiigithub]

Yes, TIM-VX supports symmetric and asymmetric quantization for the A311D chip. Thanks.