Open wzab opened 2 years ago
The approach shown in the https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/master/Interface/Streaming/axi_stream_to_master/example.cpp does not generate properly outstanding write transactions in case if the underlaying AXI interface has higher latency. Preparing the next burst is delayed until BVALID for the previous one is received. The problem is described in https://support.xilinx.com/s/question/0D52E00006w0CxZSAU/hls-maxi-interface-does-not-generate-outstanding-write-transactions
The approach shown in the https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/master/Interface/Streaming/axi_stream_to_master/example.cpp does not generate properly outstanding write transactions in case if the underlaying AXI interface has higher latency. Preparing the next burst is delayed until BVALID for the previous one is received. The problem is described in https://support.xilinx.com/s/question/0D52E00006w0CxZSAU/hls-maxi-interface-does-not-generate-outstanding-write-transactions