Introductory examples for Vitis HLS
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C/C++ synthesizable examples
| Each example comes with C/C++ source code, testbench, a README, and Tcl/Python scripts and/or config file. The examples are organized in categories denoted by the directory names: | Category | Description | Key Examples |
|---|---|---|---|
| Appnotes | A DSP design, a legacy digital up converter appnote. | Digital_Up_Converter | |
| Array | Show how to partition memory arrays. | array_partition_complete | |
| Interface | Common examples for interface protocols. | using_axi_master using_axi_lite using_axi_stream_with_side_channel_data |
|
| Misc | Other examples such as the RTL blackbox flow and the LogiCore FFT from Vivado. | fft rtl_as_blackbox |
|
| Modelling | The essentials for loops, arbitrary precision types and vectors. | basic_loops_primer using_arbitrary_precision_arith using_vectors using_array_stencil_1d |
|
| Pipelining | Illustrating one of the most fundamental concept of HLS. | hier_func pipelined_loop |
|
| Task_Level_Parallelism | Dataflow and free running streams with hls::task. |
using_stream_of_blocks input_bypass unique_task_regions using_directio_hs_in_tasks |
Running the example scripts using Vitis Unified IDE
| Script Type | Command | Notes |
|---|---|---|
| Tcl | vitis-run --mode hls --tcl run_hls.tcl|Open the directory containing run_hls.tcl as workspace after running the Tcl script to open in Vitis Unified IDE |
|
| Python | vitis -s run.py|Open the created directory w as workspace after running the python script to open in Vitis Unified IDE |
By default C Simulation, C Synthesis and Co-Simulation are run with both Tcl and Python scripts. Modify respective script to run Implementation and Packaging.
Documentation
Vitis High-Level Synthesis User Guide (UG1399)
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