Closed NicolasBondouxA closed 3 years ago
Hi,
Since you are using the 2019.2 branch, can you please once try sourcing the 2019.2 Vitis and XRT. Also, is the original example working for you (with DATA_SIZE = 256)?
Hi;
The original example works for any other value for DATA_SIZE than 1025 !
I could also reproduce the problem on AWS F1, which uses Vitis and XRT 2019.2. On F1, the process [xocl-scheduler-] uses 100% during the second run, that is blocked ; anysubsequent run will then fail.
Actually, I have that concern because my project make usage of this code example, but with random batch size; and I observed deadlocks for certain batch size. So, I tested rtl_vadd_2clks for different batch sizes and ran into the same issue. I think the problem may happen when the size of the buffer written by the FPGA is just a bit more than a XDMA burst.
Hi,
I tried to reproduce the issue. I ran the example for hw_emu u200_xdma_201830_2 after sourcing 2019.2 VITIS and XRT. I ran the example thrice but was not able to reproduce the issue. Can you please mention the steps taken by you .
Hi;
I forgot to mention that the problem does not happen in hw emulation, but only with TARGET=hw. After changing the DATA_SIZE to 1025 in host.cpp, I do:
make all TARGET=hw DEVICE=$myDevice
make check TARGET=hw DEVICE=$myDevice
and that's it Thanks,
Nicolas
Hi @NicolasBondouxA , could you please post your query to Xilinx Forum incase you are still facing the same issue? https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/bd-p/tools_v
-Heera
Hello,
How to reproduce: I took the code from the 2019.2 branch and compiled with a 2019.2 Vitis.
The problem was observed xilinx_u200_xdma_201830_2 platform, and with XRT 2020.1. When changing in the host the DATA_SIZE to 1025 and running several times the example, the process will eventually get locked (most often, two runs are enough; the first run always succeed).
Here is the xbutil query trace:
Thanks, Nicolas