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Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples
http://xilinx.github.io/Vitis_Accel_Examples/
MIT License
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U200 Errors #52

Closed lloo099 closed 3 years ago

lloo099 commented 3 years ago

Some errors have happened when I run "hello world" example Vitis version:2020.1 And git clone 2020.1 version example

`make all TARGET=hw_emu DEVICE=xilinx_u200_xdma_201830_2 HOST_ARCH=x86
mkdir -p ./_x.hw_emu.xilinx_u200_xdma_201830_2
v++ -c -k vadd -t hw_emu --platform xilinx_u200_xdma_201830_2 --save-temps  -g --temp_dir ./_x.hw_emu.xilinx_u200_xdma_201830_2  -I'src' -o'_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo' 'src/vadd.cpp'
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
    Reports: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd
    Log files: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/logs/vadd
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:35789
INFO: [v++ 60-1548] Creating build summary session with primary output /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo.compile_summary, at Fri Nov 19 13:20:35 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:20:35 2021
Running Rule Check Server on port:40579
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd/v++_compile_vadd_guidance.html', at Fri Nov 19 13:20:36 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
INFO: [v++ 60-1578]   This platform contains Device Support Archive '/opt/xilinx/platforms/xilinx_u200_xdma_201830_2/hw/xilinx_u200_xdma_201830_2.dsa'
INFO: [v++ 60-1302] Platform 'xilinx_u200_xdma_201830_2.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [v++ 60-242] Creating kernel: 'vadd'

===>The following messages were generated while  performing high-level synthesis for kernel: vadd Log file: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd/vadd/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'read1'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'read2'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd/system_estimate_vadd.xtxt
INFO: [v++ 60-586] Created _x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 38s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./build_dir.hw_emu.xilinx_u200_xdma_201830_2
v++ -l  -t hw_emu --platform xilinx_u200_xdma_201830_2 --save-temps  -g --temp_dir ./build_dir.hw_emu.xilinx_u200_xdma_201830_2  -o'./build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.link.xclbin' _x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
    Reports: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link
    Log files: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/logs/link
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:45569
INFO: [v++ 60-1548] Creating build summary session with primary output /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.link.xclbin.link_summary, at Fri Nov 19 13:21:16 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:21:16 2021
Running Rule Check Server on port:41119
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link/v++_link_vadd.link_guidance.html', at Fri Nov 19 13:21:17 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
INFO: [v++ 60-1578]   This platform contains Device Support Archive '/opt/xilinx/platforms/xilinx_u200_xdma_201830_2/hw/xilinx_u200_xdma_201830_2.dsa'
INFO: [v++ 60-1302] Platform 'xilinx_u200_xdma_201830_2.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [13:21:23] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm --target emu --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:21:25 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [13:21:25] build_xd_ip_db started: /tools/Xilinx/Vitis/2020.1/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/emu/xilinx_u200_xdma_201830_2_emu.hpfm -clkid 0 -ip /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/iprepo/xilinx_com_hls_vadd_1_0,vadd -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [13:21:27] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 823 ; free virtual = 3491
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [13:21:27] cfgen started: /tools/Xilinx/Vitis/2020.1/bin/cfgen -dmclkid 0 -r /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: vadd, num: 1  {vadd_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.out_r to DDR[1]
INFO: [SYSTEM_LINK 82-37] [13:21:29] cfgen finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 782 ; free virtual = 3451
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [13:21:29] cf2bd started: /tools/Xilinx/Vitis/2020.1/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.xsd --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --target_bd emu/emu.bd
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd emu/emu.bd -dn dr -dp /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [13:21:31] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 721 ; free virtual = 3413
INFO: [v++ 60-1441] [13:21:31] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 748 ; free virtual = 3440
INFO: [v++ 60-1443] [13:21:31] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/sdsl.dat -rtd /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/cf2sw.rtd -xclbin /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xclbin_orig.xml -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [v++ 60-1441] [13:21:32] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.93 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 811 ; free virtual = 3503
INFO: [v++ 60-1443] [13:21:32] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [v++ 60-1441] [13:21:33] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.79 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 408 ; free virtual = 3105
INFO: [v++ 60-1443] [13:21:33] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw_emu -f xilinx_u200_xdma_201830_2 -g --remote_ip_cache /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/.ipcache -s --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --log_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/logs/link --report_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link --config /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/vplConfig.ini -k /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link --emulation_mode debug_waveform --no-info --iprepo /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xo/ip_repo/xilinx_com_hls_vadd_1_0 --messageDb /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link/vpl.pb /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link

****** vpl v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [VPL 60-1032] Extracting hardware platform to /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/.local/hw_platform
[13:21:51] Run vpl: Step create_project: Started
Creating Vivado project.
[13:21:53] Run vpl: Step create_project: Completed
[13:21:53] Run vpl: Step create_bd: Started
[13:22:28] Run vpl: Step create_bd: Completed
[13:22:28] Run vpl: Step update_bd: Started
[13:22:30] Run vpl: Step update_bd: Completed
[13:22:30] Run vpl: Step generate_target: Started
[13:22:51] Run vpl: Step generate_target: Completed
[13:22:51] Run vpl: Step config_hw_emulation: Started
[13:24:10] Run vpl: Step config_hw_emulation: RUNNING...
[13:24:12] Run vpl: Step config_hw_emulation: Failed
[13:24:16] Run vpl: FINISHED. Run Status: config_hw_emulation ERROR
ERROR: [VPL 60-773] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/vivado.log', caught Tcl error:  ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-2373] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/vivado.log', caught error: ERROR: caught error: ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-2373] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/runme.log', caught error: ERROR: caught error: ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [13:24:17] Run run_link: Step vpl: Failed
Time (s): cpu = 00:03:51 ; elapsed = 00:02:44 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 3835 ; free virtual = 5704
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:120: recipe for target 'build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.xclbin' failed
make: *** [build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.xclbin] Error 1
`
lloo099 commented 3 years ago

Ok, it solved by this: export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu