Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples
http://xilinx.github.io/Vitis_Accel_Examples/
MIT License
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Problem with accessing SSD from FPGA #73

Closed omidrostamabadi closed 2 years ago

omidrostamabadi commented 2 years ago

Hello,

I have an U.2 SmartSSD CSD (userguide).

Is there a way to access the SSD (read/write) from the FPGA kernel? I am aware of P2P buffers, but as far as I know, in order to copy data from SSD to P2P buffer in FPGA DDR memory, host needs to initiate the transfer. But in my use case, I need to communicate with SSD from the FPGA kernel, without any involvement of the host CPU.

Any help would be appreciated.

heeran-xilinx commented 2 years ago

Hi @omidrostamabadi , can you please post such query to Xilinx Forum?

https://support.xilinx.com/s/topic/0TO2E000000YKYAWA4/vitis-acceleration-acceleration?language=en_US

liu-xueyang commented 2 years ago

The examples under /host/p2p_simple, /host/p2p_bandwidthand /host/p2p_overlap_bandwidth utilize the P2P connection between the FPGA and SSD and the source code includes the required API. The tests also need to run with root access