Closed EngineerFPGA closed 1 year ago
The packet generation examples for the x3 examples require the x3ntg module that is not included in this repo.
x3ntg
https://github.com/Xilinx/Vitis_Accel_Examples/blob/25db2440c2eec1911c96b38fbeb95f7b3d1d0441/x3h/combine_bw_hm_passthrough/packet_gen_python/packetGen.py#L1
It is added here: https://github.com/Xilinx/Vitis_Accel_Examples/tree/2022.2/common/X3_EMU_NTG Please take a look.
The packet generation examples for the x3 examples require the
x3ntg
module that is not included in this repo.https://github.com/Xilinx/Vitis_Accel_Examples/blob/25db2440c2eec1911c96b38fbeb95f7b3d1d0441/x3h/combine_bw_hm_passthrough/packet_gen_python/packetGen.py#L1