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Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples
http://xilinx.github.io/Vitis_Accel_Examples/
MIT License
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Would it be possible to communicate between 2 host via ethernet? #86

Closed tangyuelm closed 1 year ago

tangyuelm commented 1 year ago

Dear Authors,

Thank you for the tutorial. It is very convenient, but our project now has a new requirement about how two FPGAs from 2 different host CPUs can communicate. According to some literature, some FPGA clouds connect two host CPUs via ethernet. However, I cannot find any guide about how to do it using OpenCL host code, so I am wondering if it is feasible. If so, could you provide any reference codes or guidance? Thank you.

Best, Yue Tang

heeran-xilinx commented 1 year ago

Hi @tangyuelm , Please post your query to Xilinx Forum to get support from expert? https://support.xilinx.com/s/topic/0TO2E000000YKYAWA4/vitis-acceleration-acceleration?language=en_US

tangyuelm commented 1 year ago

Sure.